CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY (A)
E2-Digital Systems Design-IV-2020-21
0%
Previous
Course data
General
Slip Test 1 on 27 March 2021
Slip Test 1
Slip Test 2-28May2021
Assignment 1
Unit1
10-02-2021 2.20pm to 3.20pm Introduction
11-02-2021 11.30am to 12.30pm Number systems
12-02-2021 2.20pm to 3.20pm conversions-examples
17-02-2021 2.20pm to 3.20pm Complements and arithmetic operations
05-02-201 and 06-02-2021 -9.10 to 10.10 am and 2.20pm to 3.20 pm numericals on 2s complements and Boolean algebra-theorems
24-02-2021 2.20pm to 3.20pm complement of function -sum of minterms
26-02-2021 9.10 am to 10.10am Canonical forms-logic gates
26-02-2021 2.20pm to 3.20pm numericals on simplification of Boolean function
10-03-2021 2.20pm to 3.20pm k-map method
12-03-2021 9.10am to 10.10am PI-EPI-RPI-SPI-Dontcares-Examples
12-03-2021 2.20pm to 3.20pm Dontcares-K-map-POS-NAND-NOR-Implementation-Examples
17-03-2021 2.20pm to 3.20pm XOR-EXNOR-Unit 2 -Design procedure
Unit2
19-03-2021 9.10am to 10.10am Adders and subtractors
19-03-2021 2.20pm to 3.20pm adder-subtractor-BCD adder
23-03-2021 10.20 am to 11.20am Code converters-Comparator
24-03-2021 2.20pm to 3.20pm Multiplexers
2603-2021 9.10am to 10.10am Multiplexers-problems-Boolean function implementation using MUX
2603-2021 2.20pm to 3.20pm Problems-Demultiplexers
31-03-2021 2.20pm to 3.20pm Decoders
01-04-2021 11.30am to 12.30pm encoders-priority encoder-problems
Topic 3
07-04-2021 2.20pm to 3.20pm Unit3 -Introduction-Sequential circuits vs combinational circuits
08-04-2021 11.30am to 12.30pm Latches-SR Latch
09-04-2021 2.20pm to 3.20pm SR latch using NAND gates
15-04-2021 11.30am to 12.30 am Gated SR Latch and D-Latch
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210416-26- latch vs flipflop, SR Flip-flop
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210423-27-- JK-T-D-Flipflops-Race around Condition
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210429-28-Flip-flop Conversions-Examples
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210430-29- Master slave flipflop-setup and hold time
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210505-30-Registers-Shift Registers
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210506-31-Asynchronous Counters
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210507-32-Synchronous counters
Topic 4
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210508-33-ring counters-problems
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210510-34-FSM-Mealy and Moore
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210512-35-FSM in VERILOG HDL, ASM, Clock generation
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210512-36-Introduction to HDL
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210513-37-HDL-Design methodology, Basic concepts, data types
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210514-38-Gatelevel modeling, delays
Topic 5
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210517-39-Dataflow modeling and delays
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-210518-Timing control in behavioral modeling-Demo on counters -up/down and updown
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-210518-Introduction to switchlevel modeling
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NSM-20210519-43-Switch level modeling, Logic synthesis -
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM--20210520-44--tasks and functions, concept of programming FPGA-
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210521-45-Tabulation Method
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM--20210526-46-Previous question paper discussion
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210527-47-Previous question paper discussion
AY2021-UG-SEM-4-ECE2-18EC C11-DSD-NAM-20210528-48-Brief revision
Next
CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY (A)
Side panel
Log in
Username
Password
Remember username
Forgot Password?
Log in
E2-Digital Systems Design-IV-2020-21
Home
Skip to main content
Course info
Home
Courses
Electronics and Communications Engineering
UG
Academic Year 2020-21
IV Semester
E2-Digital Systems Design-IV-2020-21
Summary
E2-Digital Systems Design-IV-2020-21
Teacher:
Dr.N.Alivelu Manga Associate Professor
Skill Level
:
Beginner